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Assertions for clock enable/clock gating

 
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peterpb
Junior
Junior


Joined: Mar 18, 2004
Posts: 9

PostPosted: Tue Jul 21, 2009 10:58 pm    Post subject: Assertions for clock enable/clock gating Reply with quote

I'm trying to write assertions for clock enable features. In our design (SoC) there are several clocks with different frequencies (1, 12, 24, 48 MHz) and several "clock enable" signals. Very often there 2 or 3 clock enable signals controlling 1 clock.

Here is the code for checking if the clock is running:
Code:

property p_clk_enable;
      @(posedge clk) disable iff (!clk_en)
             $rose(tested_clk) |=> (!tested_clk);
endproperty


But the waveform is not showing that this assertion is running correctly.

How do you test that a clock is enabled (running) or disabled?

And additional questions:
1. when clock enable signal is set to 1, there is 2 clock delay; how to account for this (same for disabling a clock - 2 clock cycle delay)?
2. "assertion clk" and "tested_clock" - do they have to be in-sync?
3. when we have 2 or 3 clock enable signals they may have different timing; is this a problem?

-Peter
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vhdlcohen
Industry Expert
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Joined: Jan 05, 2004
Posts: 1291
Location: Los Angeles, CA

PostPosted: Wed Jul 22, 2009 2:34 am    Post subject: Re: Assertions for clock enable/clock gating Reply with quote

peterpb wrote:
How do you test that a clock is enabled (running) or disabled?
And additional questions:
1. when clock enable signal is set to 1, there is 2 clock delay; how to account for this (same for disabling a clock - 2 clock cycle delay)?
2. "assertion clk" and "tested_clock" - do they have to be in-sync?
3. when we have 2 or 3 clock enable signals they may have different timing; is this a problem?-
Even though SVA is great, not all assertions need to be written in SVA. The class of assertions that you're addressing are typically done, or supported with auxiliary SystemVerilog code that measures the delay between events of interest using the $time. You can also use a higher frequency clock to check for inactivity of a signal. The $stable might also be handy. It returns TRUE if the value of the expression did not change between the sampled value at the previous cycle and the sampled value at the current cycle.
There were discussions on this issue on this board, but I could not locate them. Below is a simple example that needs to be modified per your requirements.
Code:
module testtime;
  timeunit 1ns;   timeprecision 100ps;
  time t1, t2;
  logic clk1, clk2;
  always @ (posedge clk1, posedge clk2) begin
   if(clk1) // may have more case conditions here
     t1 = $time;
    if(clk2)   // may have more case conditions here
      assert ((($time -t1) >  100ns) && (($time -t1) < 125ns)) else
       $display("timing error in clk1 clk2");
  end
endmodule

_________________
Ben Cohen http://www.systemverilog.us/
* SystemVerilog Assertions Handbook, 3rd Edition, 2013
* A Pragmatic Approach to VMM Adoption
* Using PSL/SUGAR ... 2nd Edition
* Real Chip Design and Verification
* Cmpt Design by Example
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peterpb
Junior
Junior


Joined: Mar 18, 2004
Posts: 9

PostPosted: Wed Jul 22, 2009 8:52 am    Post subject: Reply with quote

Ben, thank you for quick response.
I've been trying to find "a nice, elegant SVA solution", so it's nice to hear from you (SVA expert) that SVA is not for everything.

I've searched the board back and forth. I've found several topics about clock events and clock frequency checking. Here is one of them:
http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=2469&highlight=assertion+clock

Quote:
You can also use a higher frequency clock to check for inactivity of a signal.

This is what I'm using now. Very Happy
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