How to Store n-bits at a particular State in FSM!

EEEngineer · Junior Joined: Jul 26, 2004 Posts: 8

Hello All,

I am trying to store n-bits in a particular 'State' in FSM...but the stored bits default to the immediate nit seen...

For example: the bit stream I have is : 11 00101

Say after '11' I need to store '00101' in a 5-bit register. To do this I am running a For-loop at the 3rd State but the 5-bit register stores 00000.

And on changing the bit stream to 11 100101 the stored 5-bits printed 11111 ...

So my code is omething like this:

Janick

Janick · Posted: Wed Aug 04, 2004 3:54 pm **Post subject:**

I do have a question though. I've been assuming all along that synthesizability was a requirement because of the coding style you are using and yoru first question which had a separate testbench...

If synthesizability is not a requirement, all of this can be much easier to model using behavioral code...

EEEngineer · Junior Joined: Jul 26, 2004 Posts: 8

Hello Janick,

Yes, Synthesizability is the requirement. As ultimately the code which I am writing for implementing the Host Architecture is going to go onto the Xilinx FPGA.

The main problem I am facing, as normally is the case, is that I dont have the written specification. So as a result I have to read this documentation, write a code then upgrade it with some little new functionality.

So, I would like to know the way around for the "@(CLOCK) " as you suggested that its not Synthesizable.

Another question I have is, I was wondering if there is any free CAD tool which can give me Synthesis results as one of the main requirement for my design is to minimise Register usage.

Thanx,

hemanth · Senior Joined: Aug 16, 2004 Posts: 93 Location: Bangalore

Hello there, if you want to synthesize that then you cannot have the for loops running around like that inside a clocked process. you can have a counter checking inside the third state where for each count you take in the streaming bit until its done. The counter can be run in a seperate always proc or in the same proc.
hope this helps.

bebic · Newbie Joined: Aug 15, 2004 Posts: 2

Soln 1:

S0 -> State when the '11' pattern is not yet detected
S1 -> Detected first '1' (Get back to S0 if the next bit is not a '1')
S2 -> Detected second '1'
S3 -> Heres start a counter which runs from 0 to 4 on every clock edge.
Store[count] = Stream;
Get back to state S0 when the count expires and entire stream is stored.

Soln 2:
See this as a 8 states state machine.

S0 -> State when '11' pattern is not yet detected
S1 -> Detected first '1' (Get back to S0 if the next bit is not a '1')
S2 -> Detected second '1'
S3 -> Store[0] = Stream
S4 -> Store[1] = Stream
S5 -> Store[2] = Stream
S6 -> Store[3] = Stream
S7 -> Store[4] = Stream
Get back to S0 from this state.

Regards,
Bebic