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atul_123
Senior
Joined: May 30, 2007
Posts: 134
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 Posted: Thu Oct 13, 2011 4:36 am Post subject: Can I gice x inside the constraint block of system verilog |
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Hello,
I need to constraint a variable as value x. It is defined as logic in the base class.
e.g
`ovm_do_on_with(myseq , p_sequencer.mst_sequencer[0],
{
my_seq.wr == 1'bx;
});
I get compilation error when i do this. |
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atul_123
Senior
Joined: May 30, 2007
Posts: 134
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| Posted: Thu Oct 13, 2011 4:40 am Post subject: |
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I see this error:
Invalid X or Z in state expression value for constraint |
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dave_59
Senior
Joined: Jun 22, 2004
Posts: 974
Location: Fremont, CA
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| Posted: Thu Oct 13, 2011 1:06 pm Post subject: |
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The constraint solver can only handle 2-state values.
You can either either set wr to 'x and do my_seq.wr.rand_mode(0) before calling `ovm_do_on_with(), or the preferred method is not to use the `ovm_do macro at all. Just write | Code: |
my_seq = create(...);
start_item(my_seq,,p_sequencer.mst_sequencer[0])
my_seq.randomize();
my_seq.wr='x;
finish_item(my_seq);
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Dave Rich
Mentor Graphics |
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