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Login Nickname Password Security Code: Type Security Code BACKWARD Don't have an account yet? You can create one. As a registered user you have some advantages like theme manager, comments configuration and post comments with your name. Modules · Home · Downloads · FAQ · Feedback · Recommend Us · Web Links · Your Account Advertising Who's Online There are currently, 51 guest(s) and 0 member(s) that are online. You are Anonymous user. You can register for free by clicking here    Verification Guild: Forums  Forum FAQ   Search   Usergroups   Profile  Digest    Log in  VHDL vs Verilog/SV for RTL          Verification Guild Forum Index -> Main View previous topic :: View next topic   Author Message qwk000 Senior Joined: Oct 13, 2004 Posts: 66 Location: Fort Worth, TX Posted: Thu Dec 22, 2011 11:52 am    Post subject: VHDL vs Verilog/SV for RTL Which language is best for RTL if your testbench is in System Verilog (UVM)? Back to top dave_59 Senior Joined: Jun 22, 2004 Posts: 974 Location: Fremont, CA Posted: Thu Dec 22, 2011 12:43 pm    Post subject: The best language to use is the one you have the best resources to deal with. There is very little little difference in the synthesizable subset of RTL between the two languages. If you stick with SystemVerilog, then you have only one language to maintain, and can switch easily between design and verification tasks. Back to top qwk000 Senior Joined: Oct 13, 2004 Posts: 66 Location: Fort Worth, TX Posted: Mon Jan 02, 2012 11:56 am    Post subject: I have heard from Mentor and Synopsys FAEs that Verilog/SV is recommended for RTL because of simulation efficiency. Would this be recommended because mixed language simulations have some overhead, assuming UVM or some other SV based testbench is used? Back to top dave_59 Senior Joined: Jun 22, 2004 Posts: 974 Location: Fremont, CA Posted: Mon Jan 02, 2012 12:50 pm    Post subject: Is simulation performance is an issue for you, Verilog is a better choice because that is where the majority of investment in simulator research and development goes towards. Of course you can easily write code that simulates poorly in any language, so you need to invest the time to profile and review your code. That could have much more of an impact on performance. Back to top qwk000 Senior Joined: Oct 13, 2004 Posts: 66 Location: Fort Worth, TX Posted: Tue Jan 03, 2012 3:01 pm    Post subject: Thanks Dave. Are there still safety concerns, or has the latest SV standard cleared up those issues? I have heard that some military contractors in the US require VHDL to be used because of this. I don't know if this is still true. Also, are there any standards out there that require the use of VHDL because reliability/safety? For example, DO-254. Does it require VHDL? What about European standards, etc? Back to top vhdlcohen Industry Expert Joined: Jan 05, 2004 Posts: 1237 Location: Los Angeles, CA Posted: Wed Jan 04, 2012 10:04 am    Post subject: qwk000 wrote: Are there still safety concerns, or has the latest SV standard cleared up those issues? I have heard that some military contractors in the US require VHDL to be used because of this. I don't know if this is still true. Also, are there any standards out there that require the use of VHDL because reliability/safety? For example, DO-254. Does it require VHDL? What about European standards, etc? As Dave said "There is very little little difference in the synthesizable subset of RTL between the two languages". Thus, one needs to follow simple design rules. I don't believe that SV is any safer that VHDL. One can make serious mistakes in any language; thus, the real problems are not caused by the language, but by the misunderstanding of the requirements, and the lack of a good verification environment. The use of an assertion language, like SVA, in the design process and verification, along with constraint-randomization and coverage is very important. At one time DOD required ADA because it was "safer". That requirement was GONE a long long time ago. _________________ Ben Cohen http://www.systemverilog.us/ * SystemVerilog Assertions Handbook, 3rd Edition, 2013 * A Pragmatic Approach to VMM Adoption * Using PSL/SUGAR ... 2nd Edition * Real Chip Design and Verification * Cmpt Design by Example * VHDL books Back to top dave_59 Senior Joined: Jun 22, 2004 Posts: 974 Location: Fremont, CA Posted: Wed Jan 04, 2012 1:16 pm    Post subject: DO-254 in the US and ED-80 in Europe do not mandate a particular design language. Rather they require a certifiable, documented process to trace all aspects of decisions made in a project. Both VHDL and Verilog can be used to satisfy that requirement. See http://www.mentor.com/solutions/do-254/ BTW, I wrote a paper a while back showing how you could use stronger type checking in SystemVerilog that could be used to address some of the weakness of Verilog's data types. See http://www.eetimes.com/electrical-engineers/education-training/tech-papers/4130156/Using-Strong-Types-in-Your-SystemVerilog-Design-and-Verification Dave Rich Mentor Graphics Back to top Display posts from previous: All Posts1 Day7 Days2 Weeks1 Month3 Months6 Months1 Year Oldest FirstNewest First         Verification Guild Forum Index -> Main All times are GMT - 5 Hours Page 1 of 1   Jump to: Select a forum Main----------------MainEDA NewsCommunity Services Networking----------------Looking for a jobLooking for candidates Archives----------------AssertionsCoverageFormalSimulationDesignMiscellaneous Test----------------Test  You cannot post new topics in this forum You cannot reply to topics in this forum You cannot edit your posts in this forum You cannot delete your posts in this forum You cannot vote in polls in this forum Forums ©

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