evcd - selectively include/exclude ports ($dumpports). How?

ljepson

We are generating manufacturing test vectors and using $dumpports to generate an .evcd. The recipient of the evcd has requested that we do not include power or ground ports.

How can I generate an .evcd which selectively includes ports (or selectively allows me to exclude ports)?

I somewhat recall, from past companies/projects, pulling up the waves in a viewer, removing ones I didn't want, and then saving the .vcd. (Maybe I am just dreaming here.)
Is this the standard way folks do this?

I am working with Cadence's Simvision(64) 10.20-s100 and trying the above, but am not able to export as an .evcd (sst2, vcd, and csv are choices). So I am exporting as a vcd for now. There must be a better way to do this.

Any ideas?

I'm asking Cadence and the company doing the testing, but thought I'd ask here to see if I can get a faster response.

genes · Senior Joined: Oct 06, 2008 Posts: 21

One awkward approach is to:
- Create an empty module.
- Declare an input port for every signal you want to be in the evcd file.
- Place an instance of your empty module in your testbench.
- Connect each hierarchical signal up to the corresponding empty module port.
- Use the empty module instance in the $dumpports call.

This will be a lot of work up front, but then you can avoid the manual process of going into a waveform viewer every time you run a new simulation.

ljepson · Posted: Mon Jan 09, 2012 12:25 pm **Post subject:**

Genes,

While I agree that is awkward, that is what our tester (or intermediary to the test company) has suggested.

Thanks a lot.

It'll be great when Cadence has/adds some functionality to their tools to achieve this. I wonder if Mentor, Synopsys, or Aldec have already.

(Aside: Prizes for fastest responses.
1st place - VerificationGuild
2nd place - the intermediary we work with to make test vectors (close second)
3rd place - Cadence sourcelink (still awaiting a response)
)

dave_59 · Posted: Mon Jan 09, 2012 2:35 pm **Post subject:**

Note Genes suggestion will only work if there are no bidirectional ports. The key feature of $dumpports is that it gives you strength information and determines which side of the port is driving the value on the port.

Mentor's Modelsim/Questa has a Tcl command 'vcd dumpports' that allows you to specify individual signals with wildcards, as well as force the apparent direction of the port.

chm · Posted: Thu Jan 12, 2012 3:39 am **Post subject:**

dave_59, why do you say that the wrapper would not work? The information which direction a signal goes is not lost, no matter how many levels of hierarchy it is going through.

You can certainly use the wrapper and it will work, we have done that a lot of times until we got better test pattern conversion tools which are much better at handling these things (vtran, I'm not affiliated but just a customer).

dave_59 · Posted: Thu Jan 12, 2012 10:52 am **Post subject:**

chm,

The suggestion here was an empty stub, not a wrapper. All signals will appear as inputs (from the TESTFIXTURE) when resolving signals. See LRM section 21.7.4.3.1 State characters

ljepson · Posted: Thu Jan 12, 2012 12:32 pm **Post subject:**

Yes, I have heard both ideas. I am using a wrapper now.

It'd be nice to have a separate stub instead, applied with a bind file - so that other gatelevel testbenches could more easily use it. I was going to try to snoop to drive the outputs of this stub, but wasn't sure how to deal with inout. I quickly moved to using a wrapper to get smthg working more quickly.