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    Verification Guild :: View topic - publish verilog / sv / e syntax
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    publish verilog / sv / e syntax

     
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    samitc
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    Joined: Apr 19, 2010
    Posts: 3

    PostPosted: Sun Feb 19, 2012 4:39 am    Post subject: publish verilog / sv / e syntax Reply with quote

    Is it legal to publish verilog / sv / e syntax on an internet site, or do i need a special permission Question
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    vhdlcohen
    Industry Expert
    Industry Expert


    Joined: Jan 05, 2004
    Posts: 1320
    Location: Los Angeles, CA

    PostPosted: Sun Feb 19, 2012 9:24 am    Post subject: Reply with quote

    To be on the safe side, contact the IEEE and identify which version you are publishing and why. For all my books I got permission to copy snippets of SV LRM, provided I explain the concepts with examples.

    IEEE Intellectual Property Rights Office
    445 Hoes Lane
    Piscataway, NJ 08855-1331 USA
    +1 732 562 3828 (phone)
    +1 732 562 1746 (fax)
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    Ben Cohen http://www.systemverilog.us/
    * SystemVerilog Assertions Handbook, 3rd Edition, 2013
    * A Pragmatic Approach to VMM Adoption
    * Using PSL/SUGAR ... 2nd Edition
    * Real Chip Design and Verification
    * Cmpt Design by Example
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    pavanshanbhag
    Senior
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    Joined: Mar 25, 2009
    Posts: 380
    Location: Bangalore, India

    PostPosted: Wed Feb 29, 2012 5:20 am    Post subject: Reply with quote

    Quote:

    Is it legal to publish verilog / sv / e syntax on an internet site, or do i need a special permission


    I dont think its illegal, it depends on user intrest. If it was illegal, then other friendly sites wouldn't have poped out which gives an explaination on how to use with examples.

    But, importantly none of the confidential information should be leaked. If you take care of it.. Then it should be fine.
    _________________
    -Pavan K Shanbhag

    ?The difference between genius and stupidity, genius knows his limits.? - Albert Einstein
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