Ashutosh Sharma [ashutosh_ece@rediffmail.com]

Newsletter · Original Contribution Joined: Dec 08, 2003 Posts: 1107

(Originally from Issue 3.14, Item 13.0)

From: Anonymous

Is their any advantage of verilog-XL over NC-verilog ?

Newsletter · Original Contribution Joined: Dec 08, 2003 Posts: 1107

(Originally from Issue 3.15, Item 11.0)

From: John Weiland

Verilog-XL is generally simpler to use than NC-Verilog. NC is compiled
and uses a three step process like NC-VHDL (compile, elaborate and
simulate). Verilog-XL is interpreted and requires a single command
line. There is a script that imitates XL, currently called
"ncverilog", but some options require enormously long switches to
implement. Also, NC has various types of access to internal data, all
of which are turned off by default to get the fastest speed. It's easy
to forget exactly what access you need for what you're doing at the
moment. There can also be issues with your default cds.lib file, which
isn't used but has to be error-free anyway.

All this is pretty insignificant for a power user (who should probably
use NC for any large job), but if I'm teaching Verilog to someone I
like using XL so they can concentrate on the language without getting
bogged down in the tool. After they've spent a week coding I'd go over
NC. NC is certainly faster in normal use, but mostly when some of the
code was already compiled for prior simulation (like old testbench
with new RTL, or old netlist and old library with new testbench). The
two are surprisingly similar in speed if you're dealing entirely with
brand new code.