Assertion failures and pass/fail status

PaulZ · Newbie Joined: Feb 21, 2007 Posts: 4

I’m also not finding an easy way to assign the number of assertion failures into a verilog variable using Cadence’s IUS. The main purpose for this is to add the assertion error count into our single verilog exit task to determine if the simulation passed or failed. Having a single true test pass or fail statement would save the possibility of somebody misreading “TEST PASS” when actually the test failed for an assertion early in the simulation. This would also help keep our simple regression reporting scripts from changing (e.g. tail sim.log | grep “TEST PASS”).

How do other people handle reporting assertion error summary in regressions and simulation logs? Does VCS give access to the assertion error count in verilog?

We have explored some ideas, each with pros and cons.
1) Increment a global assertion failed counter in the else action block “else global_assertion_fail_count++;”
Con: All testbenches using IP with these assertions require the global variable.
Con: Can not guarantee every designer will adhere to this methodology when using assertions –It’s hard enough to get them to use them in the first place.
Con: Can not guarantee newly acquired IP follows this convention.
2) On every failure, stop the sim and increment a TCL assertion error counter, and run the sim again.
Con: exit sim will now need to be in TCL – not portable to every simulator.
3) Print long assertion summary list either before or after exit task which has the total error count
Con: You still get a TEST PASS message even though you really failed.

hemanth · Senior Joined: Aug 16, 2004 Posts: 93 Location: Bangalore

I am not sure I understand your question properly but why dont you just terminate the simulation on an assertion failure and print out the one which failed. Isnt this much easier?

Thanks,
Hemanth

Ajeetha · Posted: Thu Feb 22, 2007 10:07 am **Post subject:**

Hi,
Some thing similar came up a while ago, search in this forum, see:

http://www.verificationguild.com/modules.php?name=Forums&file=viewtopic&t=1059
http://www.verificationguild.com/modules.php?name=Forums&file=viewtopic&t=1280
http://www.verificationguild.com/modules.php?name=Forums&file=viewtopic&t=1228

One of the approaches suggested there is via TCL, something that you
already sort of ruled out, but AFAIK all 3 major vendors can do that
for you - but enabling run time TCL means compromising on performance
in general, so I wouldn't do this for regressions.

The other is one into SystemC - may not be needed here in this topic.

The approach of VMM_LOG is the natural way to go, but just as you
mentioned - it is hard to maintain that every assertion shall follow
that.

One other, elegant solution will be to be able to customize the SVA's
$error. I know in VCS one can do this quite easily, see:
http://www.deepchip.com/items/0344-13.html

Given that it is PLI/VPI, hopefully other vendors allow this as well.

It is such a common problem and am surprised there is no straight
forward solution, a wake up call to all EDA Vendors claiming "Complete
Verification" perhaps? This is really where users spend too much time
unnecessarily, clearly EDA tools can do a better helping hand here.

HTH,
Ajeetha, CVC
www.noveldv.com
_________________
Ajeetha Kumari,
CVC Pvt Ltd. http://www.cvcblr.com
* A Pragmatic Approach to VMM Adoption http://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar

PaulZ · Newbie Joined: Feb 21, 2007 Posts: 4

PaulZ · Newbie Joined: Feb 21, 2007 Posts: 4

Adam · Industry Expert Joined: Jun 01, 2004 Posts: 159

Any word from Cadence on the ability to substitute your own $error() routine ?

This definitely would be nice. Too bad the industry seems to be moving to
general language approaches that require a lot to make the error.
_________________
Adam Krolnik
Director of Design Verification
Verisilicon Inc.
Plano TX. 75074
Co-author "Assertion-Based Design", "Creating Assertion-Based IP"