| Login | | Don't have an account yet? You can create one. As a registered user you have some advantages like theme manager, comments configuration and post comments with your name. | |
| Who's Online | There are currently, 37 guest(s) and 0 member(s) that are online.
You are Anonymous user. You can register for free by clicking here | |
 | |
|
Verification Guild: Forums |
|
| View previous topic :: View next topic |
| Author |
Message |
Newsletter Original Contribution

Joined: Dec 08, 2003 Posts: 1107
|
Posted: Fri Jan 21, 2000 12:00 am Post subject: Seeking reactions to TransEDA's VHDLCover |
|
|
(Originally from Issue 1.1, Item 6.0)
From: Laurentiu Ionescu
We can contribute with an evaluation report on VHDLCover, the code
coverage tool from TransEDA. we are in the process of purchasing it
and in the same time would like to hear more reaction on it. |
|
| Back to top |
|
 |
Newsletter Original Contribution

Joined: Dec 08, 2003 Posts: 1107
|
Posted: Fri Feb 04, 2000 12:00 am Post subject: Seeking reactions to TransEDA's VHDLCover |
|
|
(Originally from Issue 1.2, Item 5.0)
From: Zehentner Georg
One important feature of a vhdl-coverage tool is, that the results are
displayed clearly. So one can evaluate the lack of coverage and
improve the testbench. I think this is a strength of VHDL-Cover.
We are using VHDL-Cover since a long time and it runs stable and is
easy to use. There are a few restrictions about the GUI. So we
analyze and simulate via batch files or Makefiles. For result
analysis we use the GUI. |
|
| Back to top |
|
 |
|
|
You cannot post new topics in this forum You cannot reply to topics in this forum You cannot edit your posts in this forum You cannot delete your posts in this forum You cannot vote in polls in this forum
|
| |
|
|