Common testbench mistakes in VHDL

Newsletter · Original Contribution Joined: Dec 08, 2003 Posts: 1107

(Originally from Issue 1.5, Item 6.0)

From: Ben Cohen

I thought I would share some common TB mistakes and solutions, to help
others, and to hear form others about their experiences. Janick, those
were also discussed in your Writing TB book.

As a VHDL consultant, I recently found the following errors that
caused the test engineer hours of frustration for the unexplainable
errors he was getting.

1. Mishandling of clock definition. Specifically, in a 50 MHz (20 ns
period design clocked ASIC, a derived 25 MHz signal is used in the
design as an enable signal.

The following is ERRONEOUS code defined in the TB:

Clk50_Proc: process
begin
Clk50 <= '0';
wait for 10 ns;
Clk 50 <= '1';
wait for 10 ns;
end process Clk50_Proc;

Clk25_Proc: process -- BAD code for a derived clock !!!
begin
Clk25 <= '0';
wait for 20 ns;
Clk 25 <= '1';
wait for 20 ns;
end process Clk25_Proc;

The problem here is that the 25 MHz clock is not modeled as a derived clock,
like the real system. Solution:

signal Clk50 : std_logic := '1'; -- to start at '1' for a full cycle
signal Clk25 : std_logic := '1';
...
Clk50 <= not Clk50 after 10 ns; -- concurrent signal assignment

Clk25_Proc: process -- derived clock
begin
wait until Clk50 = '1';
Clk25 <= not Clk25 after 1 ns;
-- 'after' not really needed, but
-- emphasizes that this is a derived signal.
-- Also helps in debug
end process Clk25_Proc;

2. Mishandling of assignments of stimulus vectors

-- BAD design. Data changes at same edge as rising edge of clock.
-- No setup time -- will cause all kinds of errors!!!!
XY_Proc: process
begin
wait for 40 ns;
Data <= "1010";
wait for 100 ns;
DATA <= "0000";
--....
end process XY_Proc;

SOLUTION: Make assignments synchronous to the clock.

-- in declaration section or in a package:
procedure WaitNclk(Signal Clk : Std_Logic;
constant NumbClk : Positive) is
begin
for I in 1 to NumbClk loop
wait until Clk = '1';
end loop
end WaitNClk;
-- ....
-- In TB architecture
XY_Proc: process
begin
WaitNClk(Clk50, 40 ns/20 ns);
Data <= "1010" after 1 ns; -- after is optional, but preferred
WaitNClk(Clk50, 5); -- wait for 100 ns;
DATA <= "0000"; -- no after shown here
--....
end process XY_Proc;