Verification strategy wanted for DMA-based interface

Newsletter · Original Contribution Joined: Dec 08, 2003 Posts: 1107

(Originally from Issue 4.15, Item 8.0)

From: CY Tam

Our company is changing direction and would like to make a wireless
chip (802.11a/b/g with video processing power). We used to make chip
with PCI interface. Our verification environment was to build a PCI
master/slave BFM to interact with the chip. External PCI master BFM
will read a list of tasks and program the chip (register read/wirte)
via PCI cycles. The testbench is all Verilog.

For the new chip, what's good way to do this? There is no PCI
interface, the old way is not going to work. It is going to be a
problem for both Verilog simulation side and FPGA emulation side (we
use the same PCI instructions set in the FPGA chip in PCI slot). The
new chip is kind of standalone with RF frontend and DRAM interface.

Can I make a dummy internal bus model client and initialize all the
register read/write like before?