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    Verification Guild :: View topic - VHDL vs Verilog/SV for RTL
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    VHDL vs Verilog/SV for RTL

     
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    qwk000
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    PostPosted: Thu Dec 22, 2011 11:52 am    Post subject: VHDL vs Verilog/SV for RTL Reply with quote

    Which language is best for RTL if your testbench is in System Verilog (UVM)?
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    dave_59
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    PostPosted: Thu Dec 22, 2011 12:43 pm    Post subject: Reply with quote

    The best language to use is the one you have the best resources to deal with. There is very little little difference in the synthesizable subset of RTL between the two languages. If you stick with SystemVerilog, then you have only one language to maintain, and can switch easily between design and verification tasks.
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    qwk000
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    PostPosted: Mon Jan 02, 2012 11:56 am    Post subject: Reply with quote

    I have heard from Mentor and Synopsys FAEs that Verilog/SV is recommended for RTL because of simulation efficiency.

    Would this be recommended because mixed language simulations have some overhead, assuming UVM or some other SV based testbench is used?
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    dave_59
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    PostPosted: Mon Jan 02, 2012 12:50 pm    Post subject: Reply with quote

    Is simulation performance is an issue for you, Verilog is a better choice because that is where the majority of investment in simulator research and development goes towards.

    Of course you can easily write code that simulates poorly in any language, so you need to invest the time to profile and review your code. That could have much more of an impact on performance.
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    qwk000
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    PostPosted: Tue Jan 03, 2012 3:01 pm    Post subject: Reply with quote

    Thanks Dave.

    Are there still safety concerns, or has the latest SV standard cleared up those issues? I have heard that some military contractors in the US require VHDL to be used because of this. I don't know if this is still true.

    Also, are there any standards out there that require the use of VHDL because reliability/safety? For example, DO-254. Does it require VHDL? What about European standards, etc?
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    vhdlcohen
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    PostPosted: Wed Jan 04, 2012 10:04 am    Post subject: Reply with quote

    qwk000 wrote:
    Are there still safety concerns, or has the latest SV standard cleared up those issues? I have heard that some military contractors in the US require VHDL to be used because of this. I don't know if this is still true.

    Also, are there any standards out there that require the use of VHDL because reliability/safety? For example, DO-254. Does it require VHDL? What about European standards, etc?

    As Dave said "There is very little little difference in the synthesizable subset of RTL between the two languages". Thus, one needs to follow simple design rules. I don't believe that SV is any safer that VHDL. One can make serious mistakes in any language; thus, the real problems are not caused by the language, but by the misunderstanding of the requirements, and the lack of a good verification environment. The use of an assertion language, like SVA, in the design process and verification, along with constraint-randomization and coverage is very important.

    At one time DOD required ADA because it was "safer". That requirement was GONE a long long time ago.
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    dave_59
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    PostPosted: Wed Jan 04, 2012 1:16 pm    Post subject: Reply with quote

    DO-254 in the US and ED-80 in Europe do not mandate a particular design language. Rather they require a certifiable, documented process to trace all aspects of decisions made in a project. Both VHDL and Verilog can be used to satisfy that requirement. See http://www.mentor.com/solutions/do-254/

    BTW, I wrote a paper a while back showing how you could use stronger type checking in SystemVerilog that could be used to address some of the weakness of Verilog's data types. See http://www.eetimes.com/electrical-engineers/education-training/tech-papers/4130156/Using-Strong-Types-in-Your-SystemVerilog-Design-and-Verification

    Dave Rich
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