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spartanthewarrior
Senior
Joined: Aug 15, 2009
Posts: 32
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 Posted: Thu Apr 19, 2012 5:07 am Post subject: Question: Vacuous Match !! |
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//-- Property For Pipe-Line
`define true 1
property pipe_line_check;
logic [7:0] temp_data;
@(posedge clk) (`true, temp_data = stage_1) ##NUM_CLK (data_out === temp_data);
endproperty
Note:- stage_1 is a 8-Bit signal coming from first pipeline stage.
Question: Will this property will give (Vacuous Match !!), as we don't have implication operator. |
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vhdlcohen
Industry Expert
Joined: Jan 05, 2004
Posts: 1237
Location: Los Angeles, CA
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| Posted: Thu Apr 19, 2012 8:09 am Post subject: |
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A property that this a sequence is either false or true nonvacously.
An assertion that has a property as a sequence can either fail or succeed nonvacously.
_________________
Ben Cohen http://www.systemverilog.us/
* SystemVerilog Assertions Handbook, 3rd Edition, 2013
* A Pragmatic Approach to VMM Adoption
* Using PSL/SUGAR ... 2nd Edition
* Real Chip Design and Verification
* Cmpt Design by Example
* VHDL books |
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spartanthewarrior
Senior
Joined: Aug 15, 2009
Posts: 32
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| Posted: Thu Apr 19, 2012 9:32 am Post subject: |
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Thanks much !!
It clears my doubt... |
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