Formal Verification Survey

Newsletter · Original Contribution Joined: Dec 08, 2003 Posts: 1107

(Originally from Issue 4.17, Item 8.0)

From: Sebastian Jaeger

The Royal Institute of Technology, Stockholm (Sweden) and the
Darmstadt University of Technology, Darmstadt (Germany) are conducting
a web-based industry survey. The survey is part of my thesis
"Technical and Economical Barriers and Drivers for the Introduction of
Formal Methods in the Verification of Digital Systems".

It addresses all companies which perform digital, digital/analog or
HW/SW design, i.e. companies using and not (yet) applying formal
approaches.

The purpose of the survey is to develop a realistic view of the status
quo of functional formal verification in the semiconductor
industry. Among other things we want to find out about the leading
companies` verification approach, their needs and future plans, the
valuation of existing tools as well as reasons for and against the
introduction or increased use of formal methods in the design flow.

Answering the questions will take only 15 minutes. All participants
will get a free copy of the study including the survey results. In
addition your company will get the chance to be named as sponsor of
the survey free of charge. You take no risks: The data collected in
this survey will only be reported in aggregate form.

We would highly appreciate it if you could support our study by
participating in this survey by going to

http://www.formal-verification.com.

The password is "formal".

Although we know that our target group has a high workload we would be
deeply grateful for your participation within the next week if
possible.

Thank you very much and best regards

Sebastian Jaeger