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| Most Popular - Top 10% (of all 113 Links) | Show Top: [ 10 - 25 - 50 | 1% - 5% - 10% ]
| VMK: Generic Makefile generator for VHDL models
Description: A tool that peruses VHDL source code and figures out the compilation dependencies. It then generates a Makefile to compile the model in the correct order and minimize the recompilation necessary to maintain the VHDL model.
Completely tool-indenpendent. Can be used on ANY VHDL simulator.
Open source, licensed under Apache V2.0
Added on: 08-May-2007 Hits: 4232
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Category: Freeware/Tools
On-line Specman and e tutorial
Description: An overview of the e language
Added on: 01-Sep-2004 Hits: 3113
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Category: Freeware/Training
State Machine Coverage Using Specman
Description: by Jacob Joseph
Added on: 16-Nov-2004 Hits: 3027
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Category: Reference/Papers
Quick Reference Cards from Verifica
Description: Looking for a useful Quick Reference Card for Specman, Vera, Verilog or VHDL? It's available -- free -- in the Verifica Library.
Added on: 27-Dec-2003 Hits: 2736
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Category: Freeware/Training
Design Verification with e
Description: Written for both experienced and new users, Design Verification with e gives you a broad coverage of e. It stresses the practical verification perspective of e rather than emphasizing only its language aspects.
Added on: 27-Jan-2004 Hits: 2720
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Category: Reference/Books
Writing Testbenches: Functional Verification of HDL Models
Description: How to write testbenches using VHDL, Verilog, e or OpenVera.
Added on: 30-Nov-2003 Hits: 2566
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Category: Reference/Books
Specman verification blog
Description: A blog about everything HVL - including tips, bugs, coding techniques, personal experiences and personal traumas - with special emphasis on Specman-e and SystemVerilog for verification
Added on: 18-Feb-2006 Hits: 2552
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Category: Freeware/Training
Design And Reuse, The Web's System-On-Chip Design Resource
Description: D&R provides a global collaboration network for sharing design resources in the electronics SoC industry.
Added on: 31-Mar-2004 Hits: 2530
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Category: Freeware/IP
FPGA Central: FPGA Events, Forums, IP, Vendors, News, Webcast
Description: FPGA Central is created to provide a central place for FPGA Vendors & Users to share experiences and information about FPGA Design, Development, Verification, Validation, Process, Tools & Products.
Added on: 21-Sep-2007 Hits: 2509
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Category: Reference/Communities
Specman Yahoo! Group
Description: Yahoo! group for Specman users
Added on: 14-Dec-2003 Hits: 2448
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Category: Reference/Communities
Assertion-Based Design, Second Edition
Description: Text focuses on assertion-based design, showing how to specify assertions, create and adopt a methodology that supports assertion-based design, and what to do with the assertions and methodology once you have them. Discusses multiple forms of assertion specification, such as Accellera Open Verification Library (OVL).
Added on: 26-Aug-2004 Hits: 2436
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Category: Reference/Books
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