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Category: Main/Freeware/Tools
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VMK: Generic Makefile generator for VHDL models
Description: A tool that peruses VHDL source code and figures out the compilation dependencies. It then generates a Makefile to compile the model in the correct order and minimize the recompilation necessary to maintain the VHDL model.
Completely tool-indenpendent. Can be used on ANY VHDL simulator.
Open source, licensed under Apache V2.0
Added on: 08-May-2007 Hits: 2163
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Veripool
Description: Free, open-source tools for Verilog and SystemC
Added on: 19-Jul-2004 Hits: 2056
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Verilog 2 HTML translator
Description: Translate en entire Verilog model into a set of annotated HTML files that allow the code to be browsed.
Added on: 15-Sep-2004 Hits: 941
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Teal Open Source Verification Library
Description: Teal is an Open-Source, free library for verification in C++. It has all the basics of verification, stable random number generation, threads, 4-state arbitrary length registers and conection to the DUT. It supports either pli 1.0 or 2.0 and has been compiled with mti,vcs, aldec, and Icarus on Linux, Solarus, and Windows (not all possible combinations).
Added on: 23-Feb-2005 Hits: 1705
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ImportViewer shows the import graph of an e program
Description: ImportViewer helps you visualize and explore the import graph of an e program. As a part of the Aspect Oriented modeling paradigm, files are being given an important role in the structure of an E program. The import statement is the way to declare that a module relies on the declarations of another. It guarantees that the imported module is loaded before the importing module. Thus an import statement declares a direct dependency between two modules.
Added on: 06-Nov-2005 Hits: 850
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